Course Description-Computer Organisation and Architecture | Parallel Computing | Central Processing Unit

  Course Description Course Name: Computer Organization and Architecture Course Code: 15B11CI313 Total Course Credit: 5 (L=3, T=1, P=2) Course Credits Theory: 4 (L=3, T=1, P=0) Course Credit Practical: 1 (L=0, T=0, P=2) Course Type: CORE Branch and Semester: B.Tech. (CSE) IIIrd Semester Session: July  – December 2017 Instructors: Padam Kumar, Pawan K. Upadhyay, Hema N., Amarjeet Kaur, Kashav Ajmera, Taj Alam, Introduction All students of computing should acquire some understanding and appreciation of a computer system’s functional components, their characteristics, their performance, and their interactions. Students need to understand computer architecture in order to structure a program so that it runs more efficiently on a real machine. The course provides an overview of computer architecture and teaches students the operation of a typical computing machine. It covers the basic principles, while acknowledging the complexity of existing commercial systems. The format of the course will be lecture-discussions, assignments. Students are strongly encouraged to participate actively in class discussions.   Course Objective   1)   To become familiar in following topics: a.   How Computer Systems work & its basic principles b.   How to analyze the system performance. c.   Concepts behind advanced pipelining techniques. d.   The current state of art in memory system design e.   How I/O devices are being accessed and its principles. 2)   To provide the knowledge on Instruction Level Parallelism Course Outcomes    To apply the knowledge of performance metrics to find the performance of systems.    To create an assembly language program to program a microprocessor system.    To design a hardware component for an embedded system.    To deal with different types of computers.    To identify high performance architecture design.    To identify the problems in components of computer.    To develop independent learning skills and be able to learn more about different computer architectures and hardware.    To learn & use the new technologies in computers.  Teaching Methodology The class will combine lectures, tutorials and labs. Lectures will focus on learning the concepts and principles, and in lab sessions students will have to work individually as well as in groups who will  jointly be assigned combined tasks on related problems. Focus will be on problems in the application domain of other courses being studied by the students. Overall the course will adopt a problem-solving approach using different simulators. The topics will be discussed in an integrated manner following the principles of problem based learning. Tools and Techniques Logic Simulator, Manosim, 8085 Simulator, MASM for 8086. *All theoretical concepts and numerical will be tested through the above-mentioned emulator or simulator. Course Outlines S.NO. Topic and Subtopics Lecture(s) 1 INTRODUCTION: Levels in architecture, Virtual machine, Evolution of multi-level machines. 02 2 PERFORMANCE MEASURES FOR COMPUTER SYSTEM 03 3   CPU ORGANIZATION: Data-path and control, Instruction execution, Microinstruction, Hardwired and micro-programmed control, ISA: Instruction Set Architecture, Stack/accumulator/register-register/register-memory type of architecture, Memory addressing, Types of instruction, Data movement, Arithmetic/logic, Control flow, Addressing modes, Instruction format, MIPS and 8085 architecture, Assembly language programming, Assembler, Case study of 8086 and Assembly language programming. 18 4 MEMORY ORGANIZATION: Hierarchal memory structure, Cache memory and organization. 10 5 I/O ORGANIZATION: Programmed/Interrupt driven I/O, Direct memory access 05 6 INTRODUCTION TO PIPELINING 04 Total 42 Evaluation Scheme Assessment Scheme Marks *Test 1 Examination *Test 2 Examination 20 20 # Final Examination 35 ~ Internal Assessment (Continuous Evaluation) [Assignments, Surprise Quizzes and Project] 25 Total 100 A student will need to get at least 22 marks out of a maximum of 75 (total) in the tests and 30 marks out of 100 in the overall total to be considered passed.  Course Objectives (Post-conditions) Knowledge Objectives At the conclusion of the course, following learning objectives are expected to be achieved: 1.   You will broaden your knowledge of contemporary computer architectures. 2.   You will become aware of the contemporary computer organization. 3.   You will increase your proficiency in performance evaluation of processors. 4.   You will know how to design computer memory chips efficiently. 5.   You will know the design principles of contemporary computers. 6.   You will acquire the background for understanding next-generation CPUs. 7.   You will learn about Parallel Organizations  – Parallel Processing and Multi Core Computers 8.   You will learn how to design the pipeline for uniprocessor and multiprocessor systems. 9.   You will learn concepts associated with distributed, grid and cluster computing 10.   You will learn data centre architecture and case study of supercomputers. Application Objectives The homework portions of the course are intended to help you apply your understanding, 1.   to design memory system of contemporary computers. 2.   to understand and be able to explain bus transactions, memory organization and address decoding, basic I/O   interfaces and port addressing.   3.   to understand how to write micro programmed control sequence for processors.   4.   to understand the design principles for distributed computing. 5.   to lay a foundation for pursuing some additional career options in computer manufacturing organizations. Text Book M. Morris Mano, Computer System Architecture, Prentice Hall of India Pvt Ltd, Fourth edition, 2002. ISBN: 81-203-0855-7. Reference Books 1.   William Stallings, Computer Organization and Architecture  – Designing for Performance, 9th Edition, Pearson Education, 2013. 2.   Nicholas Carter, Schaum’s outline of Computer Architecture, Tata McGraw Hill, 2006, 3.   John L. Hennessy and David A Patterson, Computer Architecture A quantitative Approach, Morgan Kaufmann / Elsevier, Fourth Edition, 2007 Resources Lecture presentations and assignments will be posted on the student resource from time to time. In addition following additional online/downloadable resources will be useful. 1)   http://nptel.ac.in/courses/Webcourse-contents/IIT-%20Guwahati/comp_org_arc/web/ 2)   http://cs.nyu.edu/~gottlieb/courses/2010s/2011-12-fall/arch/class-notes.html 3)   http://www.cse.iitm.ac.in/~vplab/courses/comp_org/LEC_INTRO.pdf 4)   http://www.cs.iastate.edu/~prabhu/Tutorial/title.html 5)   http://www.cag.csail.mit.edu/ 6)   http://www.research.ibm.com/compsci/arch/   Assignments Assignment plan to include one assignment per week will be posted on the student resource separately. Students will be expected to submit the assignment as per expected time plan. Ethics During the course, students are expected to adhere to ethical standards expected of a professional. Any work you turn in has to be your own, written up by you personally. Honest behavior is expected at all times. Good Luck on the course. Course Faculty Contact Information *Professor Padam Kumar Dean (R, I & D) padam.kumar@jiit.ac.in Mr. Pawan K. Upadhyay pawan.upadhyay@jiit.ac.in Ms. Hema N. Assistant Professor hema.n@jiit.ac.in Ms. Amarjeet Kaur Assistant Professor amarjeet.kaur@jiit.ac.in Mr. Kashav Ajmera Assistant Professor kashav.ajmera@jiit.ac.in Dr. Taj Alam (Course Coordinator) Assistant Professor taj.alam@jiit.ac.in Department of CS and IT Jaypee Institute of Information Technology A-10, Sector-62, Noida-201307, Uttar Pradesh, INDIA *Chief Course Coordinator